A compact, light-weight, power-saving liquid crystal display device is generally used as a display monitor of a car navigation system which provides positional information of a car and various driving guide information. Such a display device is not only used as the monitor of the car navigation system, but also often used as a monitor for displaying television pictures.
FIG. 11 is a block diagram showing an example of the structure of a conventional driving circuit for an active matrix driving-type liquid crystal display device using a TFT (thin film transistor) as a switching element.
A signal generating circuit 60 includes a PLL circuit 50. The PLL circuit 50 is formed by a phase comparator 50a, an integrator 50b, a voltage control oscillator (VCO) 50c, and a divider (H counter) 50d. A composite synchronizing signal CSYN is input as an input signal to the PLL circuit 50. The voltage control oscillator 50c oscillates a signal at a frequency corresponding to a horizontal synchronizing signal HSYN of the input composite synchronizing signal CSYN. The oscillated signal is input to the divider 50d. The divider 50d generates a timing signal in a horizontal direction using the oscillated signal as a clock. The timing signal is output to a decoding circuit 51 from the divider 50d.
The decoding circuit 51 converts the timing signal into a source driver controlling signal, and also generates a signal CKV to be output to a divider (V counter) 52. The divider 52 uses the signal CKV as a clock to generate a timing signal in a vertical direction, and outputs the timing signal to a decoding circuit 53. The divider 52 is reset by a vertical synchronizing signal VSYN of the composite synchronizing signal CSYN, and operated based on the vertical synchronizing signal VSYN as a reference. The decoding circuit 53 converts the timing signal output from the divider 52 into a gate driver control signal. More specifically, the gate driver control signal is composed of two signals, SPS, and CLS. Both of the signals SPS and CLS are output to a gate driver 54 from the decoding circuit 53. The gate driver 54 controls a vertical direction for switching the TFT.
The source driver control signal generated by the decoding circuit 51 is used for sampling and holding data, and is composed of two signals SPD and CLD. The signal SPD is an initiation control signal for controlling the initiation of sampling. The signal CLD is a sampling pulse timing signal. Both of the signals SPD and CLD are output to a shift register of a source driver 55 from the decoding circuit 51. Each unit of the shift register generates one sampling pulse every horizontal scanning period based on both the signals SPD and CLD, and outputs the sampling pulse to a sample-and-hold circuit 58, to be described later, in the source driver 55.
FIG. 12 is a view explaining a simplified structure of the sample-and-hold circuit 58 in the source driver 55. The number of the sample-and-hold circuits 58 is the same as the number of source bus lines SL in a liquid crystal panel 56 shown in FIG. 11. A video signal Vs used exclusively for a liquid crystal (TFT) is input to each of the sample-and-hold circuit 58. The polarity of the video signal Vs is inverted every horizontal scanning period and every vertical scanning period so as to prevent the application of a direct-current voltage to the liquid crystal and flicker on the display.
The voltage of the video signal Vs is charged in a sampling capacitor C1 during the time in which a switch SW1 is opened by a sampling pulse. The charged voltage is held for one horizontal scanning period, and then transferred to a holding capacitor C2 when a switch SW2 is opened by a transfer pulse. The transferred voltage is output as a signal voltage to the source bus lines SL in the liquid crystal panel 56 through an impedance converter (output buffer) 59.
As illustrated in FIG. 11, in the liquid crystal panel 56, a number of gate bus lines (horizontal scanning lines) GL and a number of source bus lines SL are arranged to cross each other. One pixel 57 is formed in each region enclosed by adjacent gate bus lines GL and adjacent source bus lines SL. The pixels 57 as a whole are arranged in a matrix form. Formed in each pixel 57 are a TFT as a switching element, and a pixel electrode for applying the signal voltage to the liquid crystal. In each pixel 57, the gate of the TFT is connected to the gate bus line GL and the pixel electrode is connected to the source bus line SL through the drain and source of the TFT.
Moreover, the liquid crystal panel 56 includes a striped color filter in which red, green, and blue filters are alternately and repeatedly formed as stripes. A sequence of adjacent three pixels 57 function as a pixel indicating red, a pixel indicating green, and a pixel indicating blue, respectively, thereby forming one set of dots for display.
A pulse for switching the TFT on is output to the gate bus line GL from a shift register in the gate driver 54 in synchronism with the output of the signal voltage to the source bus lines SL from the source driver 55. A signal voltage is applied only to the pixel 57 located on the gate bus line GL to which the ON pulse is input, and the pixel 57 holds this voltage for an OFF period (one vertical scanning period). By repeating this process from the first line through the last line of the gate bus lines GL, a picture in one vertical scanning period is displayed.
In the case when the video signal Vs input to the sample-and-hold circuit 58 is a continuously varying signal (analog signal) such as a television broadcast signal, sampling is performed by time-division by which the display range of the input video signal Vs is divided at time intervals corresponding to the number of dots in the liquid crystal panel 56 as shown in FIG. 13. In FIG. 13, voltages V1, V2, and V3 in the first line (one horizontal scanning period) of the video signal Vs are sampled by sampling pulses S1, S2, and S3, respectively. Voltages -V1, -V2, and -V3 in the second line (one horizontal scanning period) of the video signal Vs are sampled by sampling pulses S4, S5, and S6, respectively. In the case of the above-mentioned sampling pulses, S1 and S4 are sampling pulses produced by one circuit. Similarly, S2 and S5 are produced by one circuit, and S3 and S6 are produced by one circuit. In this sampling method, the video signal Vs and the sampling pulses S1 to S6 are not directly synchronized using a data latch circuit, for example. Moreover, since the color filter of the liquid crystal panel 56 has striped alignments, the timing of sampling is always in phase in the respective lines (horizontal scanning periods).
However, if a liquid crystal display device incorporating the above-mentioned driving circuit is used as a display device capable of being used with both a television receiver and a navigation system designed for use in an automobile, the following drawbacks arise.
In the case when the video signal Vs input to the sample-and-hold circuit 58 is a set of discrete signals like digital signals output by a computer, for example, if the video signal Vs and the sampling pulse Sa has, for example, the phase relationship between Vs1 and Sa1 shown in FIG. 14, a voltage Vd is charged in the sampling capacitor C1. However, if the video signal Vs and the sampling pulse Sa has the phase relationship between Vs2 and Sa2, for example, no voltage is charged in the sampling capacitor C1. Consequently, no voltage is applied to the liquid crystal, and a proper display cannot be achieved. For instance, if an attempt is made to display a vertical line at the timing of the video signal Vs2, the vertical line is not displayed.
Thus, in the conventional driving system, when the sampling pulse Sa and the video signal Vs as data are out of phase, sampling cannot be performed, and loss of data sometimes occurred on the display. For instance, data loss sometimes occurred as described above when the video signal Vs was a digital signal output by a computer and data (360 dots in a horizontal direction) was slightly greater than the number of dots on a panel (320 dots in a horizontal direction).